Energy-Efficient Digital Circuit Design using Threshold Logic Gates

Energy-Efficient Digital Circuit Design using Threshold Logic Gates

abstract: Improving energy efficiency has always been the prime objective of the custom and automated digital circuit design techniques. As a result, a multitude of methods to reduce power without sacrificing performance have been proposed. However, as the field of design automation has matured over...

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Bibliographic Details
Other Authors: Kulkarni, Niranjan (Author)
Format: Doctoral Thesis
Language:English
Published: 2015
Subjects:
Computer science
Electrical engineering
ASIC
clock skew
FPGA
low power
threshold logic
Online Access:http://hdl.handle.net/2286/R.I.36457

Internet

http://hdl.handle.net/2286/R.I.36457

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