Fault Tolerant Network-on-Chip Router Architectures for Multi-Core Architectures
As the feature size scales down to deep nanometer regimes, it has enabled the designers to fabricate chips with billions of transistors. The availability of such abundant computational resources on a single chip has made it possible to design chips with multiple computational cores, resulting in the...
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| Language: | en_US |
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The University of Arizona.
2014
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| Online Access: | http://hdl.handle.net/10150/338752 |