AN HEURISTIC SEARCH APPROACH TO TEST SEQUENCE GENERATION FOR AHPL (A HARDWARE PROGRAMMING LANGUAGE) DESCRIBED SYNCHRONOUS SEQUENTIAL CIRCUITS

Bibliographic Details
Main Author:	Belt, John Edward, 1933-
Language:	en_US
Published:	The University of Arizona. 1973
Subjects:	Digital integrated circuits > Testing. Logic circuits > Testing. Electric fault location > Data processing. AHPL (Computer program language)
Online Access:	http://hdl.handle.net/10150/288052

id	ndltd-arizona.edu-oai-arizona.openrepository.com-10150-288052
record_format	oai_dc
spelling	ndltd-arizona.edu-oai-arizona.openrepository.com-10150-2880522015-11-22T03:00:43Z AN HEURISTIC SEARCH APPROACH TO TEST SEQUENCE GENERATION FOR AHPL (A HARDWARE PROGRAMMING LANGUAGE) DESCRIBED SYNCHRONOUS SEQUENTIAL CIRCUITS Belt, John Edward, 1933- Digital integrated circuits -- Testing. Logic circuits -- Testing. Electric fault location -- Data processing. AHPL (Computer program language) 1973 text Dissertation-Reproduction (electronic) http://hdl.handle.net/10150/288052 29290577 7320626 .b31102852 en_US Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. The University of Arizona.
collection	NDLTD
language	en_US
sources	NDLTD
topic	Digital integrated circuits -- Testing. Logic circuits -- Testing. Electric fault location -- Data processing. AHPL (Computer program language)
spellingShingle	Digital integrated circuits -- Testing. Logic circuits -- Testing. Electric fault location -- Data processing. AHPL (Computer program language) Belt, John Edward, 1933- AN HEURISTIC SEARCH APPROACH TO TEST SEQUENCE GENERATION FOR AHPL (A HARDWARE PROGRAMMING LANGUAGE) DESCRIBED SYNCHRONOUS SEQUENTIAL CIRCUITS
author	Belt, John Edward, 1933-
author_facet	Belt, John Edward, 1933-
author_sort	Belt, John Edward, 1933-
title	AN HEURISTIC SEARCH APPROACH TO TEST SEQUENCE GENERATION FOR AHPL (A HARDWARE PROGRAMMING LANGUAGE) DESCRIBED SYNCHRONOUS SEQUENTIAL CIRCUITS
title_short	AN HEURISTIC SEARCH APPROACH TO TEST SEQUENCE GENERATION FOR AHPL (A HARDWARE PROGRAMMING LANGUAGE) DESCRIBED SYNCHRONOUS SEQUENTIAL CIRCUITS
title_full	AN HEURISTIC SEARCH APPROACH TO TEST SEQUENCE GENERATION FOR AHPL (A HARDWARE PROGRAMMING LANGUAGE) DESCRIBED SYNCHRONOUS SEQUENTIAL CIRCUITS
title_fullStr	AN HEURISTIC SEARCH APPROACH TO TEST SEQUENCE GENERATION FOR AHPL (A HARDWARE PROGRAMMING LANGUAGE) DESCRIBED SYNCHRONOUS SEQUENTIAL CIRCUITS
title_full_unstemmed	AN HEURISTIC SEARCH APPROACH TO TEST SEQUENCE GENERATION FOR AHPL (A HARDWARE PROGRAMMING LANGUAGE) DESCRIBED SYNCHRONOUS SEQUENTIAL CIRCUITS
title_sort	heuristic search approach to test sequence generation for ahpl (a hardware programming language) described synchronous sequential circuits
publisher	The University of Arizona.
publishDate	1973
url	http://hdl.handle.net/10150/288052
work_keys_str_mv	AT beltjohnedward1933 anheuristicsearchapproachtotestsequencegenerationforahplahardwareprogramminglanguagedescribedsynchronoussequentialcircuits AT beltjohnedward1933 heuristicsearchapproachtotestsequencegenerationforahplahardwareprogramminglanguagedescribedsynchronoussequentialcircuits
_version_	1718133555976994816

AN HEURISTIC SEARCH APPROACH TO TEST SEQUENCE GENERATION FOR AHPL (A HARDWARE PROGRAMMING LANGUAGE) DESCRIBED SYNCHRONOUS SEQUENTIAL CIRCUITS

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