Analysis domain truncation of interconnections in multilayer packaging structures

• Main Author: Garg, Nitin Kumar, 1967-
• Other Authors: Prince, John L.
• Language: en_US
• Published: The University of Arizona. 1989
• Subjects: Integrated circuits.; Electric interference.
• Online Access: http://hdl.handle.net/10150/277078

Interconnect lines, which connect components on a chip, can exhibit transmission line properties. Several factors like decrease in size of components, and decrease in spacing between interconnect lines, have contributed to the increase in importance of interconnect lines. A circuit-analysis approach that does not include the effect of these lines may be useless for highly dense chips. The presence of an active line does not require the analysis of all the other lines in a transmission-line system. In this thesis, a numerical experimental approach based on several industry-typical geometries is used to discuss analysis domain truncation of parallel conductors lying on a horizontal plane. It is found that "The maximum analysis domain between parallel conductors lying on a horizontal plane can be deduced from the analysis of the case of several similar, and parallel conductors of smallest possible width lying on a horizontal plane." UAC (University of Arizona Capacitance Calculator) is used as the TEM parameter extractor, while UACSL (University of Arizona Coupled Line Simulator With Linear Terminations) is used to calculate the voltages on the transmission lines.