Design and timing analysis of wave pipelined circuits
In conventional pipelined circuits there is only one data wave active in any pipeline stage at any time; therefore, the clock speed of the circuit is limited by the maximum stage delay in the circuit. In wave pipelining, the clock speed depends mostly on the difference between the longest and shorte...
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| Format: | Others |
| Language: | en_US |
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Wichita State University
2006
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| Online Access: | http://hdl.handle.net/10057/383 |