Post-mapping Topology Rewriting for FPGA Area Minimization

Post-mapping Topology Rewriting for FPGA Area Minimization

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Circuit designers require Computer-Aided Design (CAD) tools when compiling designs into Field Programmable Gate Arrays (FPGAs) in order to achieve high quality results due to the complexity of the compilation tasks involved. Technology mapping is one critical step in the FPGA CAD flow. The final map...

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Bibliographic Details
Main Author: Chen, Lei
Language:en
Published: 2009
Subjects:
topology rewriting
FPGA
area minimization
Electrical and Computer Engineering
Online Access:http://hdl.handle.net/10012/4601

Internet

http://hdl.handle.net/10012/4601

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