Micro-operation perturbations in chip level fault modeling
In chip level testing using hardware description language approach, a difficult question to answer is: What is the best micro-operation perturbation for modeling fault at the chip level? In this thesis, an automatic evaluation system is developed to determine the best micro-operation perturbation. T...
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| Format: | Others |
| Language: | en_US |
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Virginia Polytechnic Institute and State University
2017
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| Online Access: | http://hdl.handle.net/10919/80061 |