| Summary: | Over the last two decades, chip design has been conducted at the register transfer (RT) Level
using Hardware Descriptive Languages (HDL), such as VHDL and Verilog. The modeling at
the behavioral level not only allows for better representation and understanding of the design,
but also allows for encapsulation of the sub-modules as well, thus increasing productivity.
Despite these benefits, validating a RTL design is not necessarily easier. Today, design
validation is considered one of the most time and resource consuming aspects of hardware
design. The high costs associated with late detection of bugs can be enormous. Together
with stringent time to market factors, the need to guarantee the correct functionality of the
design is more critical than ever.
The work done in this thesis tackles the problem of RTL design validation and presents new
frameworks for functional test generation. We use branch coverage as our metric to evaluate
the quality of the generated test stimuli. The initial effort for test generation utilized simulation based techniques because of their scalability with design size and ease of use. However,
simulation based methods work on input spaces rather than the DUT's state space and often
fail to traverse very narrow search paths in large input spaces. To encounter this problem and
enhance the ability of test generation framework, in the following work in this thesis, certain
design semantics are statically extracted and recurrence relationships between different variables are mined. Information such as relations among variables and loops can be extremely
valuable from test generation point of view. The simulation based method is hybridized with
Z3 based symbolic backward execution engine with feedback among different stages. The
hybridized method performs loop abstraction and is able to traverse narrow design paths
without performing costly circuit analysis or explicit loop unrolling. Also structural and
functional unreachable branches are identified during the process of test generation. Experimental results show that the proposed techniques are able to achieve high branch coverage
on several ITC'99 benchmark circuits and their modified variants, with significant speed up
and reduction in the sequence length. === Master of Science
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