Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution
Over the last two decades, chip design has been conducted at the register transfer (RT) Level using Hardware Descriptive Languages (HDL), such as VHDL and Verilog. The modeling at the behavioral level not only allows for better representation and understanding of the design, but also allows for e...
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Virginia Tech
2015
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| Online Access: | http://hdl.handle.net/10919/55815 |