A Modular Flow for Rapid FPGA Design Implementation

A Modular Flow for Rapid FPGA Design Implementation

This dissertation proposes an alternative FPGA design compilation flow to reduce the back-end time required to implement an FPGA design to below the level at which the user's attention is lost. To do so, this flow focuses on enforcing modular design for both productivity and code reuse, while m...

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Bibliographic Details
Main Author: Love, Andrew R.
Other Authors: Electrical and Computer Engineering
Format: Others
Published: Virginia Tech 2015
Subjects:
FPGA Productivity
Modular Design
Instant Gratification
Attention Span
Design Assembly Flow
Online Access:http://hdl.handle.net/10919/51608

Internet

http://hdl.handle.net/10919/51608

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