Computation of parasitics in multilayer hybrid microelectronics

• Main Author: Marchand, Roger T.
• Other Authors: Electrical Engineering
• Format: Others
• Language: en
• Published: Virginia Tech 2014
• Subjects: LD5655.V855 1992.M3725; Electric circuits; Microelectronics
• Online Access: http://hdl.handle.net/10919/46135; http://scholar.lib.vt.edu/theses/available/etd-12052009-020108/

Layout parasitics result from electromagnetic interaction between circuit metalizations used to connect devices on the hybrid circuit. Three linked programs have been written to calculate the capacitance and inductance between circuit metalizations. (1) XT Editor A user friendly hybrid circuit layout editor which enables the user to create circuit layouts and select portions of the circuit for parasitic computation. (2) XT Mesh A two and three dimensional fully automatic mesh generator. The mesh generator combines the quadrant/octant subdivision method and Watson's algorithm in a four step process. Initial triangulations are created and cell compatibility is ensured using an alternating initial mesh scheme. This method produces substantial time savings by avoiding the use of data tree structures and stringent cell size rules. (3) XT Field Solver A two and three dimensional finite element quasi-TEM solver which calculates the capacitance and inductance between circuit metalizations. === Master of Science