Computation of parasitics in multilayer hybrid microelectronics
Layout parasitics result from electromagnetic interaction between circuit metalizations used to connect devices on the hybrid circuit. Three linked programs have been written to calculate the capacitance and inductance between circuit metalizations. (1) XT Editor A user friendly hybrid circuit lay...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en |
| Published: |
Virginia Tech
2014
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10919/46135 http://scholar.lib.vt.edu/theses/available/etd-12052009-020108/ |