VHDL modeling of ASIC power dissipation
Accurate predict of ASIC power diss ion is possible using VHDL. By using physical data types, timing and power estimations can be based on estimated typical fan-in and fan-out conditions and a pre-characterized circuit library. Actual load conditions can be back annotated to yield actual power dissi...
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| Format: | Dissertation |
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Virginia Tech
2014
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| Online Access: | http://hdl.handle.net/10919/45224 http://scholar.lib.vt.edu/theses/available/etd-10222009-124831/ |
| Summary: | Accurate predict of ASIC power diss ion is
possible using VHDL. By using physical data types, timing
and power estimations can be based on estimated typical
fan-in and fan-out conditions and a pre-characterized
circuit library. Actual load conditions can be back
annotated to yield actual power dissipation. Methods to
determine pattern sensitive and pattern insensitive power
diss ion are presented. This approach uses the concept
of load ports VHDL to permit self determining load
conditions based on historical wiring data for a given
technology.
<p>Modeling techniques for VHDL circuit descriptions are
developed that allow propagation delay, output rise and fall
time, power dissipation be determined from VHDL event
simulation. An example of an ALU such as the 74LS181 is
presented. === Master of Science |
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