Hierarchical test generation for VHDL behavioral models

• Main Author: Pan, Bi-Yu
• Other Authors: Electrical Engineering
• Format: Others
• Language: en
• Published: Virginia Tech 2014
• Subjects: LD5655.V855 1992.P36; Integrated circuits > Very large scale integration > Computer simulation; VHDL (Computer hardware description language)
• Online Access: http://hdl.handle.net/10919/44559; http://scholar.lib.vt.edu/theses/available/etd-09052009-040449/

In this thesis, several techniques for the test generation of VHDL behavioral models are proposed. An algorithm called HBTG, Hierarchical Behavioral Test Generator, is developed and implemented to systematically generate tests for VHDL behavioral models. HBTG accepts the Process Model Graph and the precomputed tests for the individual processes of the model from which it constructs a test sequence that exercises the model hierarchically. The construction of the test sequence is automatic if the tests for the individual processes of the model are provided. The test sequence derived can be used for the simulation of the model. By comparing the simulation outputs with the data sheet or the design specifications of the corresponding circuit, a user can tell if the functionality of the model is as expected or any functional faults exist. Simulation results and conclusions are given. Some suggestions for further improvements of the program are discussed. === Master of Science