Hierarchical test generation for VHDL behavioral models

Hierarchical test generation for VHDL behavioral models

In this thesis, several techniques for the test generation of VHDL behavioral models are proposed. An algorithm called HBTG, Hierarchical Behavioral Test Generator, is developed and implemented to systematically generate tests for VHDL behavioral models. HBTG accepts the Process Model Graph and the...

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Bibliographic Details
Main Author: Pan, Bi-Yu
Other Authors: Electrical Engineering
Format: Others
Language:en
Published: Virginia Tech 2014
Subjects:
LD5655.V855 1992.P36
Integrated circuits > Very large scale integration > Computer simulation
VHDL (Computer hardware description language)
Online Access:http://hdl.handle.net/10919/44559
http://scholar.lib.vt.edu/theses/available/etd-09052009-040449/

Internet

http://hdl.handle.net/10919/44559
http://scholar.lib.vt.edu/theses/available/etd-09052009-040449/

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