Experimental results on aliasing errors in circular BIST design
<p>The circular BIST design is a technique in which the existing circuit is modified, so that the processes of test generation and response compaction are carried out by the circuit being tested itself. Most response compaction techniques suffer from loss of information, known as aliasing. Ali...
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| Format: | Others |
| Language: | en |
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Virginia Tech
2014
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| Online Access: | http://hdl.handle.net/10919/42137 http://scholar.lib.vt.edu/theses/available/etd-04182009-041213/ |
| Summary: | <p>The circular BIST design is a technique in which the existing circuit is modified, so that the
processes of test generation and response compaction are carried out by the circuit being tested
itself. Most response compaction techniques suffer from loss of information, known as aliasing.
Aliasing is said to occur in a response compaction technique when the response generated by the
circuit, under the presence of a fault, is different from its fault-free response, but this
information is later lost during compaction, and the faulty compacted response at the end of the
test session is identical to the fault-free compacted response.</p>
<p>
A program to synthesize circular BIST hardware on general sequential circuits has been
developed. A parallel fault simulator has been developed to detect aliasing errors in circular
BIST design. Experimental results on aliasing probability in circular BIST design are reported
for twenty-three sequential benchmark circuits.
</p> === Master of Science |
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