Planar Packaging and Electrical Characterization of High Temperature SiC Power Electronic Devices
This thesis examines the packaging of high-temperature SiC power electronic devices. Current-voltage measurements were conducted on as-received and packaged SiC power devices. The planar structure was introduced and developed as a substitution for traditional wire-bonding vertical structure. The pla...
Main Author: | Yue , Naili |
---|---|
Other Authors: | Materials Science and Engineering |
Format: | Others |
Language: | en |
Published: |
Virginia Tech
2014
|
Subjects: | |
Online Access: | http://hdl.handle.net/10919/36278 http://scholar.lib.vt.edu/theses/available/etd-12182008-231247/ |
Similar Items
-
Quality inspection and reliability study of solder bumps in packaged electronic devices: using laser ultrasound and finite element methods
by: Yang, Jin
Published: (2009) -
Low-Temperature Sintering of Nanoscale Silver Paste for Semiconductor Device Interconnection
by: Bai, Guofeng
Published: (2014) -
Thermomechanical Reliability of Low-Temperature Sintered Attachments on Direct Bonded Aluminum (DBA) Substrate for High-Temperature Electronics Packaging
by: Lei, Guangyin
Published: (2014) -
UBM Formation on Single Die/Dice for Flip Chip Applications
by: Jittinorasett, Suwanna
Published: (2014) -
Solderjet bumping packaging technique optimization for the miniaturization of laser devices
by: P. Ribes-Pleguezuelo, et al.
Published: (2017-11-01)