Enhancing SAT-based Formal Verification Methods using Global Learning
With the advances in VLSI and System-On-Chip (SOC) technology, the complexity of hardware systems has increased manifold. Today, 70% of the design cost is spent in verifying these intricate systems. The two most widely used formal methods for design verification are Equivalence Checking and Model Ch...
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Virginia Tech
2014
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| Online Access: | http://hdl.handle.net/10919/32987 http://scholar.lib.vt.edu/theses/available/etd-05192004-144000 |