Incremental Design Techniques with Non-Preemptive Refinement for Million-Gate FPGAs

Incremental Design Techniques with Non-Preemptive Refinement for Million-Gate FPGAs

This dissertation presents a Field Programmable Gate Array (FPGA) design methodology that can be used to shorten the FPGA design-and-debug cycle, especially as gate counts increase to many millions. Core-based incremental placement algorithms, in conjunction with fast interactive routing, are invest...

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Bibliographic Details
Main Author: Ma, Jing
Other Authors: Electrical and Computer Engineering
Format: Others
Published: Virginia Tech 2014
Subjects:
Incremental Design
Design Tool
FPGA
Placement
Online Access:http://hdl.handle.net/10919/26016
http://scholar.lib.vt.edu/theses/available/etd-01202003-151943/

Internet

http://hdl.handle.net/10919/26016
http://scholar.lib.vt.edu/theses/available/etd-01202003-151943/

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