UPSET TRENDS IN FLIP-FLOP DESIGNS AT DEEP SUBMICRON TECHNOLOGIES
Advances in fabrication technologies for semiconductor integrated circuits (ICs) have resulted in sub-100 nm feature sizes. Along with this desired reduction in dimension has come an undesired increase in vulnerability of flip-flops to soft errors, which are caused by energetic particles that either...
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| Format: | Others |
| Language: | en |
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VANDERBILT
2010
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| Online Access: | http://etd.library.vanderbilt.edu/available/etd-09062010-120803/ |