Improved bufferless routing via balanced pipeline stages
Network-on-chip (NoC) architectures with emerging interconnect technologies have been developed to meet the demand for high-performance computational systems while maintaining energy efficiency. The introduction of deflection routing and bufferless router architectures offers smaller area and lower...
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| Format: | Others |
| Language: | en |
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VANDERBILT
2013
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| Online Access: | http://etd.library.vanderbilt.edu/available/etd-07072013-145648/ |