Dynamically controlling the clock frequency based on the variations in the voltage
A digital logic circuit tends to become slower if the voltage (VDD) level drops below the normal VDD level. Because of this, the required data will not have settled before the arrival of the clock edge. This results in an incorrect sampling of the data leading to a functional failure of the chip. Th...
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| Format: | Others |
| Language: | English |
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2010
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| Online Access: | http://hdl.handle.net/2152/ETD-UT-2010-08-2010 |