Thermal and mechanical analysis of interconnect structures in 3D stacked packages
Physical scaling limits of microelectronic devices and the need to improve electrical performance have driven significant research and development into 3D architecture. The development of die stacks in first level packaging is one of the more viable short-term options for improved performance. Place...
Main Author: | |
---|---|
Format: | Others |
Language: | English |
Published: |
2011
|
Subjects: | |
Online Access: | http://hdl.handle.net/2152/ETD-UT-2010-05-993 |
id |
ndltd-UTEXAS-oai-repositories.lib.utexas.edu-2152-ETD-UT-2010-05-993 |
---|---|
record_format |
oai_dc |
spelling |
ndltd-UTEXAS-oai-repositories.lib.utexas.edu-2152-ETD-UT-2010-05-9932015-09-20T16:56:50ZThermal and mechanical analysis of interconnect structures in 3D stacked packagesWakil, Jamil Abdul3D stacked packagesThermalMechanicalModelingTSVTransientInterfacial resistanceThrough-silicon viasPhysical scaling limits of microelectronic devices and the need to improve electrical performance have driven significant research and development into 3D architecture. The development of die stacks in first level packaging is one of the more viable short-term options for improved performance. Placement of memory die above or below processors in a traditional flip chip C4 package with through-silicon vias (TSVs) has significant benefits in reducing data and power transmission paths. However, with the electrical performance benefits come great thermal and mechanical challenges. There are two key objectives for this work. The first is understanding of the die-die interface resistance, R[subscript dd], composed of the back end of line (BEOL) layers and micro-C4 interconnects. The interfacial resistance between BEOL material layers, the impact of TSVs and the impact of strain on R[subscript dd] are subtopics. The second key objective is the understanding of package thermal and mechanical behavior under operating conditions, such as local thermal disturbances. To date, these topics have not been adequately addressed in the literature. It is found that R[subscript dd] can be affected by TSVs, and that the interfacial contributions predicted by theoretical sub-continuum models can be significantly different than measurements. Using validated finite element models, the significance of the power distribution and R[subscript dd] on the temporal responses of 2D vs. 3D packages is highlighted. The results suggest local thermal hotspots can greatly exacerbate the thermal penalty due to the R[subscript dd] and that no peaks in stress arise in the transient period from power on to power off.text2011-01-07T21:36:00Z2011-01-07T21:36:06Z2011-01-07T21:36:00Z2011-01-07T21:36:06Z2010-052011-01-07May 20102011-01-07T21:36:06Zthesisapplication/pdfhttp://hdl.handle.net/2152/ETD-UT-2010-05-993eng |
collection |
NDLTD |
language |
English |
format |
Others
|
sources |
NDLTD |
topic |
3D stacked packages Thermal Mechanical Modeling TSV Transient Interfacial resistance Through-silicon vias |
spellingShingle |
3D stacked packages Thermal Mechanical Modeling TSV Transient Interfacial resistance Through-silicon vias Wakil, Jamil Abdul Thermal and mechanical analysis of interconnect structures in 3D stacked packages |
description |
Physical scaling limits of microelectronic devices and the need to improve electrical performance have driven significant research and development into 3D architecture. The development of die stacks in first level packaging is one of the more viable short-term options for improved performance. Placement of memory die above or below processors in a traditional flip chip C4 package with through-silicon vias (TSVs) has significant benefits in reducing data and power transmission paths. However, with the electrical performance benefits come great thermal and mechanical challenges. There are two key objectives for this work. The first is understanding of the die-die interface resistance, R[subscript dd], composed of the back end of line (BEOL) layers and micro-C4 interconnects. The interfacial resistance between BEOL material layers, the impact of TSVs and the impact of strain on R[subscript dd] are subtopics. The second key objective is the understanding of package thermal and mechanical behavior under operating conditions, such as local thermal disturbances. To date, these topics have not been adequately addressed in the literature. It is found that R[subscript dd] can be affected by TSVs, and that the interfacial contributions predicted by theoretical sub-continuum models can be significantly different than measurements. Using validated finite element models, the significance of the power distribution and R[subscript dd] on the temporal responses of 2D vs. 3D packages is highlighted. The results suggest local thermal hotspots can greatly exacerbate the thermal penalty due to the R[subscript dd] and that no peaks in stress arise in the transient period from power on to power off. === text |
author |
Wakil, Jamil Abdul |
author_facet |
Wakil, Jamil Abdul |
author_sort |
Wakil, Jamil Abdul |
title |
Thermal and mechanical analysis of interconnect structures in 3D stacked packages |
title_short |
Thermal and mechanical analysis of interconnect structures in 3D stacked packages |
title_full |
Thermal and mechanical analysis of interconnect structures in 3D stacked packages |
title_fullStr |
Thermal and mechanical analysis of interconnect structures in 3D stacked packages |
title_full_unstemmed |
Thermal and mechanical analysis of interconnect structures in 3D stacked packages |
title_sort |
thermal and mechanical analysis of interconnect structures in 3d stacked packages |
publishDate |
2011 |
url |
http://hdl.handle.net/2152/ETD-UT-2010-05-993 |
work_keys_str_mv |
AT wakiljamilabdul thermalandmechanicalanalysisofinterconnectstructuresin3dstackedpackages |
_version_ |
1716821128367833088 |