Process variation aware low power buffer design

Process variation aware low power buffer design

In many digital designs there is a need to use multi-stage tapered buffers to drive large capacitive loads. These buffers contribute a significant percentage of overall power. In this thesis, we propose two novel tunable buffer designs that enable reduction in power in the presence of process variat...

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Bibliographic Details
Main Author: Lok, Mario Chichun
Format: Others
Language:English
Published: 2010
Subjects:
Low power design
Adaptive circuit
Statistical sizing
Tunable circuit
Adaptable optimization
Online Access:http://hdl.handle.net/2152/ETD-UT-2010-05-1167
id ndltd-UTEXAS-oai-repositories.lib.utexas.edu-2152-ETD-UT-2010-05-1167
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spelling ndltd-UTEXAS-oai-repositories.lib.utexas.edu-2152-ETD-UT-2010-05-11672015-09-20T16:55:21ZProcess variation aware low power buffer designLok, Mario ChichunLow power designAdaptive circuitStatistical sizingTunable circuitAdaptable optimizationIn many digital designs there is a need to use multi-stage tapered buffers to drive large capacitive loads. These buffers contribute a significant percentage of overall power. In this thesis, we propose two novel tunable buffer designs that enable reduction in power in the presence of process variation. A strategy to derive the optimal buffer size and the optimal tuning rule in post-silicon phase is developed. By comparing several tunable buffer circuit topologies, we also demonstrate the tradeoffs in tunable buffer topology selection as a function of switching activity, timing requirements, and the magnitude of process variations. Using HSPICE simulations based on the high performance 32nm ASU Predictive Model, we show that up to 30% average power reduction can be achieved for a SRAM word-line decoder while maintaining the same timing yield.text2010-10-26T21:09:38Z2010-10-26T21:09:44Z2010-10-26T21:09:38Z2010-10-26T21:09:44Z2010-052010-10-26May 20102010-10-26T21:09:44Zthesisapplication/pdfhttp://hdl.handle.net/2152/ETD-UT-2010-05-1167eng
collection NDLTD
language English
format Others
sources NDLTD
topic Low power design
Adaptive circuit
Statistical sizing
Tunable circuit
Adaptable optimization
spellingShingle Low power design
Adaptive circuit
Statistical sizing
Tunable circuit
Adaptable optimization
Lok, Mario Chichun
Process variation aware low power buffer design
description In many digital designs there is a need to use multi-stage tapered buffers to drive large capacitive loads. These buffers contribute a significant percentage of overall power. In this thesis, we propose two novel tunable buffer designs that enable reduction in power in the presence of process variation. A strategy to derive the optimal buffer size and the optimal tuning rule in post-silicon phase is developed. By comparing several tunable buffer circuit topologies, we also demonstrate the tradeoffs in tunable buffer topology selection as a function of switching activity, timing requirements, and the magnitude of process variations. Using HSPICE simulations based on the high performance 32nm ASU Predictive Model, we show that up to 30% average power reduction can be achieved for a SRAM word-line decoder while maintaining the same timing yield. === text
author Lok, Mario Chichun
author_facet Lok, Mario Chichun
author_sort Lok, Mario Chichun
title Process variation aware low power buffer design
title_short Process variation aware low power buffer design
title_full Process variation aware low power buffer design
title_fullStr Process variation aware low power buffer design
title_full_unstemmed Process variation aware low power buffer design
title_sort process variation aware low power buffer design
publishDate 2010
url http://hdl.handle.net/2152/ETD-UT-2010-05-1167
work_keys_str_mv AT lokmariochichun processvariationawarelowpowerbufferdesign
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