Process variation aware low power buffer design
In many digital designs there is a need to use multi-stage tapered buffers to drive large capacitive loads. These buffers contribute a significant percentage of overall power. In this thesis, we propose two novel tunable buffer designs that enable reduction in power in the presence of process variat...
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| Format: | Others |
| Language: | English |
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2010
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| Online Access: | http://hdl.handle.net/2152/ETD-UT-2010-05-1167 |