Techniques to minimize circuitry and improve efficiency for defect tolerance

• Main Author: Rab, Muhammad Tauseef
• Format: Others
• Language: en_US
• Published: 2013
• Subjects: Defect tolerance; 3-D ICs; Redundancy; Yield
• Online Access: http://hdl.handle.net/2152/21926

As technology continues to scale to smaller geometries and newer dimensions (3-D), with increasingly complex manufacturing processes, the ability to reliably manufacture 100% defect-free circuitry becomes a significant challenge. While implementing additional circuitry to improve yield is economically justifiable, this thesis addresses the cost of defect tolerance by providing lower cost solutions or alternatively more defect tolerance for the same cost in state-of-the-art ICs, including three-dimensional ICs (3-D ICs). Conventional defect tolerance techniques involve incorporating redundancy into the design. This thesis introduces novel designs to maximize the utility of spare elements with minimal circuitry overhead, thereby improving the yield. One idea proposed is Selective Row Partitioning (SRP), a technique which allows a single spare column to be used to repair multiple defective cells in multiple columns. This is done by selectively decoding the row address bits when generating the select signals for the column multiplexers. This logically segments the spare column allowing it to replace different columns in different partitions of the row address space. All the chips are identical, but fuses are used to customize the row decoding circuitry on a chip-by-chip basis. An implementation procedure and results are presented which show improvement in overall yield at a minimal overhead cost. Moreover, new yield-enhancing design techniques for 3-D ICs are introduced. When assembling a 3-D IC, there are several degrees of freedom including which die are stacked together, in what order, and with what rotational symmetry. This thesis describes strategies for exploiting these degrees of freedom to reduce the cost and complexity of implementing defect tolerance. One strategy is to enable asymmetric repair capability within a 3-D memory stack by exploiting the degree of freedom that the order of the die in the stack can be selected. This technique optimizes the number of fuses, and in some cases, the number of spares as well, required to implement defect tolerance. Another innovative technique is to exploit rotational symmetry of the dies to do implicit reconfiguration to implement defect tolerance. Results show that leakage power and performance overhead for defect tolerance can be significantly reduced by this technique. === text