Test plan generation technique for complex integrated circuits
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ndltd-UTEXAS-oai-repositories.lib.utexas.edu-2152-116142015-09-20T16:59:54ZTest plan generation technique for complex integrated circuitsLee, SongjunIntegrated circuits--TestingIntegrated circuits--Design and construction--Cost effectivenessNot availabletext2011-06-09T21:47:57Z2011-06-09T21:47:57Z2002-122011-06-09electronichttp://hdl.handle.net/2152/11614engCopyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.Restricted |
collection |
NDLTD |
language |
English |
format |
Others
|
sources |
NDLTD |
topic |
Integrated circuits--Testing Integrated circuits--Design and construction--Cost effectiveness |
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Integrated circuits--Testing Integrated circuits--Design and construction--Cost effectiveness Lee, Songjun Test plan generation technique for complex integrated circuits |
description |
Not available === text |
author |
Lee, Songjun |
author_facet |
Lee, Songjun |
author_sort |
Lee, Songjun |
title |
Test plan generation technique for complex integrated circuits |
title_short |
Test plan generation technique for complex integrated circuits |
title_full |
Test plan generation technique for complex integrated circuits |
title_fullStr |
Test plan generation technique for complex integrated circuits |
title_full_unstemmed |
Test plan generation technique for complex integrated circuits |
title_sort |
test plan generation technique for complex integrated circuits |
publishDate |
2011 |
url |
http://hdl.handle.net/2152/11614 |
work_keys_str_mv |
AT leesongjun testplangenerationtechniqueforcomplexintegratedcircuits |
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1716821479131185153 |