High-Level Synthesis Framework for Crosstalk Minimization in VLSI ASICs

High-Level Synthesis Framework for Crosstalk Minimization in VLSI ASICs

Capacitive crosstalk noise can affect the delay of a switching signal or induce a glitch on a static signal causing timing violations or chip failure. Crosstalk noise depends on coupling parasitics, driver strength, signal timing characteristics, and signal transition patterns. Layout level crosstal...

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Bibliographic Details
Main Author: Sankaran, Hariharan
Format: Others
Published: Scholar Commons 2008
Subjects:
Crosstalk noise
Simulated Annealing
Floorplan driven high-level synthesis
Bus-based design
Macro-cell based design
Coupling parasitics
American Studies
Arts and Humanities
Online Access:https://scholarcommons.usf.edu/etd/487
https://scholarcommons.usf.edu/cgi/viewcontent.cgi?article=1486&context=etd

Internet

https://scholarcommons.usf.edu/etd/487
https://scholarcommons.usf.edu/cgi/viewcontent.cgi?article=1486&context=etd

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