Field-programmable gate-array (FPGA) implementation of low-density parity-check (LDPC) decoder in digital video broadcasting - second generation satellite (DVB-S2)

Field-programmable gate-array (FPGA) implementation of low-density parity-check (LDPC) decoder in digital video broadcasting - second generation satellite (DVB-S2)

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In recent years, LDPC codes are gaining a lot of attention among researchers. Its near-Shannon performance combined with its highly parallel architecture and lesser complexity compared to Turbo-codes has made LDPC codes one of the most popular forward error correction (FEC) codes in most of the rece...

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Bibliographic Details
Main Author: Loi, Kung Chi Cinnati
Other Authors: Salt, Eric J.
Format: Others
Language:en
Published: University of Saskatchewan 2010
Subjects:
FPGA
DVB-S2
LDPC
Online Access:http://library.usask.ca/theses/available/etd-09222010-120119/

Internet

http://library.usask.ca/theses/available/etd-09222010-120119/

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