Design tradeoff analysis of floating-point adder in FPGAs
Field Programmable Gate Arrays (FPGA) are increasingly being used to design high end computationally intense microprocessors capable of handling both fixed and floating-point mathematical operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking...
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| Format: | Others |
| Language: | en |
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University of Saskatchewan
2005
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| Online Access: | http://library.usask.ca/theses/available/etd-08182005-161614/ |