Implementing the Load Slice Core on a RISC-V based microarchitecture
As cores have become better at exposing Instruction-Level Parallelism (ILP), they have become bigger, more complex, and consumes more power. These cores are approaching the Power- and Memory-wall quickly. A new microarchitecture proposed by Carlson et. al claims to solve these problems. They claim t...
| Main Authors: | , |
|---|---|
| Format: | Others |
| Language: | English |
| Published: |
Uppsala universitet, Datorarkitektur och datorkommunikation
2020
|
| Subjects: | |
| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-424385 |