Design and Acceleration of Linear Integer System Solver on Programmable SoC

Design and Acceleration of Linear Integer System Solver on Programmable SoC

A simple solver for linear integer systems is designed and accelerated on aCycloneV SoC chip that contains Cortex-A based MCU, programmable FPGA, andinter-connect bridges. The solver is designed based on the Gaussian Elimination method, where a system coefficient matric is converted to a Row-Echelo...

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Bibliographic Details
Main Author: Gandhi, Jagadeep Ram
Format: Others
Language:English
Published: Uppsala universitet, Institutionen för informationsteknologi 2019
Subjects:
Engineering and Technology
Teknik och teknologier
Online Access:http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-390022
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spelling ndltd-UPSALLA1-oai-DiVA.org-uu-3900222019-08-03T04:30:32ZDesign and Acceleration of Linear Integer System Solver on Programmable SoCengGandhi, Jagadeep RamUppsala universitet, Institutionen för informationsteknologi2019Engineering and TechnologyTeknik och teknologier A simple solver for linear integer systems is designed and accelerated on aCycloneV SoC chip that contains Cortex-A based MCU, programmable FPGA, andinter-connect bridges. The solver is designed based on the Gaussian Elimination method, where a system coefficient matric is converted to a Row-Echelon matrix and performing back Back-Substitution to solve system variables. The matrix conversion is implemented in the FPGA with serial and parallel architectures, where the processing of two equations is performed using single and multiple reducer modules. In comparison with the software-based solver, the solver with hardware based-based matrix conversion modules are faster by at least 75% despite very high MCU clock and data transfer overhead between the subsystems. Student thesisinfo:eu-repo/semantics/bachelorThesistexthttp://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-390022IT ; 19013application/pdfinfo:eu-repo/semantics/openAccess
collection NDLTD
language English
format Others
sources NDLTD
topic Engineering and Technology
Teknik och teknologier
spellingShingle Engineering and Technology
Teknik och teknologier
Gandhi, Jagadeep Ram
Design and Acceleration of Linear Integer System Solver on Programmable SoC
description A simple solver for linear integer systems is designed and accelerated on aCycloneV SoC chip that contains Cortex-A based MCU, programmable FPGA, andinter-connect bridges. The solver is designed based on the Gaussian Elimination method, where a system coefficient matric is converted to a Row-Echelon matrix and performing back Back-Substitution to solve system variables. The matrix conversion is implemented in the FPGA with serial and parallel architectures, where the processing of two equations is performed using single and multiple reducer modules. In comparison with the software-based solver, the solver with hardware based-based matrix conversion modules are faster by at least 75% despite very high MCU clock and data transfer overhead between the subsystems.
author Gandhi, Jagadeep Ram
author_facet Gandhi, Jagadeep Ram
author_sort Gandhi, Jagadeep Ram
title Design and Acceleration of Linear Integer System Solver on Programmable SoC
title_short Design and Acceleration of Linear Integer System Solver on Programmable SoC
title_full Design and Acceleration of Linear Integer System Solver on Programmable SoC
title_fullStr Design and Acceleration of Linear Integer System Solver on Programmable SoC
title_full_unstemmed Design and Acceleration of Linear Integer System Solver on Programmable SoC
title_sort design and acceleration of linear integer system solver on programmable soc
publisher Uppsala universitet, Institutionen för informationsteknologi
publishDate 2019
url http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-390022
work_keys_str_mv AT gandhijagadeepram designandaccelerationoflinearintegersystemsolveronprogrammablesoc
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