High Level Synthesis of FPGA-Based Digital Filters
This thesis work is aimed at the high level synthesis of FPGA based IIR digital filters using Vivado HLS produced by Xilinx and HDL coder produced by MathWorks. The Higher Layer Model of the filter was designed in Vivado HLS, MATLAB and Simulink. Simulations, verification and Synthesis of the RTL co...
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| Format: | Others |
| Language: | English |
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Uppsala universitet, Institutionen för informationsteknologi
2014
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-232414 |