Design of a 5.8 GHz Multi-Modulus Prescaler
A 64-modulus prescaler operating at 5.8 GHz has been designed in a 0.18 μm CMOS process. The prescaler uses a four-phase high-speed ÷4 circuit at the input, composed of two identical cascaded ÷2 circuits implemented in pseudo-NMOS. The high-speed divider is followed by a two-bits phase switching sta...
| Main Author: | |
|---|---|
| Format: | Others |
| Language: | English |
| Published: |
Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon
2006
|
| Subjects: | |
| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9324 |