Optimisation of a Pipeline ADC by using a low power, high resolution Flash ADC as backend.
Flash ADCs with resolutions from 3 to 5 bits have been implemented on a transistor level. These ADCs are to be incorporated as the backend of a higher resolution Pipeline ADC. The motivation for this work has been to see how much the resolution of this backend can be increased before the power consu...
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| Format: | Others |
| Language: | English |
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Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon
2008
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8924 |