Design of Low-Power Reduction-Trees in Parallel Multipliers

Design of Low-Power Reduction-Trees in Parallel Multipliers

Multiplications occur frequently in digital signal processing systems, communication systems, and other application specific integrated circuits. Multipliers, being relatively complex units, are deciding factors to the overall speed, area, and power consumption of digital computers. The diversity of...

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Bibliographic Details
Main Author: Oskuii, Saeeid Tahmasbi
Format: Doctoral Thesis
Language:English
Published: Norges teknisk-naturvitenskapelige universitet, Fakultet for informasjonsteknologi, matematikk og elektroteknikk 2008
Subjects:
parallel multiplier
multi-operand adder
partial product reduction tree
arithmetic equivalency
progressive design
low power
transition activity
dynamic power
static or leakage power
total power
wallace
dadda
full-adder
half-adder
combinational logic
gate-level
Electrical engineering
Elektroteknik
Online Access:http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-1958
http://nbn-resolving.de/urn:isbn:978-82-471-7166-0

Internet

http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-1958
http://nbn-resolving.de/urn:isbn:978-82-471-7166-0

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