Low Power Gain Cell Arrays: Voltage Scaling and Leakage Reduction
In this thesis, a fully logic - compatible Gain - Cell (GC) based Dynamic - Random - Access (DRAM) with a storage capacity of 2048 bit is designed in UMC – 180 nm technology. The GC used is a two transistor PMOS (2PMOS) cell. This thesis aims at building the foundation for further research on the ef...
| Main Author: | |
|---|---|
| Format: | Others |
| Language: | English |
| Published: |
Linköpings universitet, Elektroniksystem
2012
|
| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-73970 |