Low Power and Area Efficient Semi-Digital PLL Architecture for High Brandwidth Applications
The main scope of this thesis is to implement a new architecture of a high bandwidth phase-locked loop (PLL) with a large operating frequency range from 100~MHz to 1~GHz in a 150~$nm$ CMOS process. As PLL is the time-discrete system, the new architecture is mathematically modelled in the z-domain. T...
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| Format: | Others |
| Language: | English |
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Linköpings universitet, Elektroniksystem
2011
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71029 |