Design and Evaluation of High Density 5T SRAM Cache for Advanced Microprocessors
This thesis presents a five-transistor SRAM intended for the advanced microprocessor cache market. The goal is to reduce the area of the cache memory array while maintaining competitive performance. Various existing technologies are briefly discussed with their strengths and weaknesses. The design m...
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| Format: | Others |
| Language: | English |
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Linköpings universitet, Institutionen för systemteknik
2004
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2286 |