Utilizing FPGAs for data acquisition at high data rates
The aim of this thesis was to configure an FPGA with high speed ports to capture data from a prototype 4 bit ΣΔ analogue-to-digital converter sending data at a rate of 2.4 Gbps in four channels and to develop a protocol for transferring the data to a PC for analysis. Data arriving in the four channe...
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| Format: | Others |
| Language: | English |
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Linköpings universitet, Elektroniska komponenter
2009
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-17820 |