Konstruktion av förstärkare och insamplingssteg till en PSAADC i 0.25 um CMOS

Konstruktion av förstärkare och insamplingssteg till en PSAADC i 0.25 um CMOS

The aim and goal of this work has been to design and implement a voltage reference network for a 12-bit PSAADC, Parallell Successive Analog to Digital Converter. A chip containing the design has been sent away for fabrication. Because of the long processing time, no measurement data are presented. T...

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Bibliographic Details
Main Author: Andersson, Martin
Format: Others
Language:Swedish
Published: Linköpings universitet, Institutionen för systemteknik 2002
Subjects:
Electronics
ADC
SAADC
PSAADC
OP
miller-op
OTA
voltage references
tvåstegsförstärkare
Elektronik
Online Access:http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1132
Description
Summary:The aim and goal of this work has been to design and implement a voltage reference network for a 12-bit PSAADC, Parallell Successive Analog to Digital Converter. A chip containing the design has been sent away for fabrication. Because of the long processing time, no measurement data are presented. The main specifications for the voltage reference generator is to generate stable reference voltages with low noise and a good PSRR. Efforts has also been made to minimize the power consumption.

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