Design of a High-Speed CMOS Comparator
This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3.3 V. The comparator is designed for time-interleaved band...
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| Format: | Others |
| Language: | English |
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Linköpings universitet, Institutionen för systemteknik
2007
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10446 |