Minimizing Test Time through Test FlowOptimization in 3D-SICs
3D stacked ICs (3D-SICs) with multiple dies interconnected by through-silicon-vias(TSVs) are considered as a technology driver and proven to have overwhelming advantagesover traditional ICs with a single die in a package in terms of performance, powerconsumption and silicon overhead. However, these...
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| Format: | Others |
| Language: | English |
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Linköpings universitet, Programvara och system
2013
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-102171 |