Graph dominators in logic synthesis and verification
This work focuses on the usage of dominators in circuit graphs in order to reduce the complexity of synthesis and verification tasks. One of the contributions of this thesis is a new algorithm for computing multiple-vertex dominators in circuit graphs. Previous algorithms, based on single-vertex dom...
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| Format: | Others |
| Language: | English |
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KTH, Mikroelektronik och informationsteknik, IMIT
2004
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4293 |