Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture

Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture

Three-Dimensional (3D) integration of circuits based on die and wafer stacking using through-silicon-via is a critical technology in enabling "more-than-Moore", i.e. functional integration of devices beyond pure scaling ("more Moore"). In particular, the scaling from multi-core t...

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Bibliographic Details
Main Author: Weldezion, Awet Yemane
Format: Doctoral Thesis
Language:English
Published: KTH, Industriell och Medicinsk Elektronik 2016
Subjects:
Alpha-model
Average distance
B-Model
NoC
Zero-load predictive model
deflection routing
q-routing
Online Access:http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-179694
http://nbn-resolving.de/urn:isbn:978-91-7595-803-3

Internet

http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-179694
http://nbn-resolving.de/urn:isbn:978-91-7595-803-3

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