Study of Timing Yield Optimization and Rectilinear Polygon Generation Algorithm
With the decreasing of integrate circuit’s feature size, the process parameters of chips have serious variations. The process variations have severe influence on the timing analysis of integrate circuit. The precise modeling of process variations is the prerequisite of statistical timing analysis. I...
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| Format: | Others |
| Language: | English |
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KTH, Skolan för informations- och kommunikationsteknik (ICT)
2011
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-121588 |