Functional Verification of Arithmetic Circuits using Linear Algebra Methods
This thesis describes an efficient method for speeding up functional verification of arithmetic circuits namely linear network such as wallace trees, counters using linear algebra techniques. The circuit is represented as a network of half adders, full adders and inverters, and modeled as a system...
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| Format: | Others |
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ScholarWorks@UMass Amherst
2011
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| Online Access: | https://scholarworks.umass.edu/theses/657 https://scholarworks.umass.edu/cgi/viewcontent.cgi?article=1796&context=theses |