Fault tolerant nanoscale microprocessor design on semiconductor nanowire grids

• Main Author: Wang, Teng
• Language: ENG
• Published: ScholarWorks@UMass Amherst 2009
• Subjects: Electrical engineering
• Online Access: https://scholarworks.umass.edu/dissertations/AAI3349747

As CMOS manufacturing technology approaches fundamental limits, researchers are looking for revolutionary technologies beyond the end of the CMOS roadmap. Recent progress on devices, nano-manufacturing, and assembling of nanoscale structures is driving researchers to explore possible new fabrics, circuits and architectures based on nanoscale devices. Several fabric architectures based on various nanoscale devices have been proposed for nanoscale computation. These show great advantages over conventional CMOS technology but focus on FPGA-style applications. There has been no work shown for nanoscale architectures tuned for a processor application. This dissertation proposes a novel nanowire-based 2-D fabric referred to as Nanoscale Application-Specific IC (NASIC). Compared with other nanoscale fabric architectures, NASIC designs can be optimized for higher density and performance in an application-specific way (similar to ASIC in this aspect) and used as a fabric for processors. We present the design of a wire-streaming processor (WISP-0), which exercises many NASIC circuit styles and optimizations. A major goal of NASIC, and for other nanoscale architectures, is to preserve the density advantage of underlying nanodevices. Topological, doping and interconnect constraints can severely impact the effective density that can be achieved at the system level. To handle these constraints, we propose a comprehensive set of optimizations at both circuit and logic levels. Evaluations show that with combined optimizations, WISP-0 is still 39X denser than the equivalent design in 18nm CMOS technology (expected in 2018 by ITRS). Another key challenge for nanoscale computing systems is dealing with the unreliable nanodevices. The defect rate of nanodevices is expected to be orders of magnitude higher than what we are accustomed to with conventional CMOS processing based on lithography. In this dissertation, we first investigate various sources of defects/faults in NASIC circuits and analyze their impacts. Then, a hierarchical, multi-layer solution is proposed to tolerate defects/faults. Simulation shows that the yield of WISP-0 is as high as 50% even if as many as 15% transistors are defective. Estimations of the speed, power consumption of NASIC designs are also presented.