A tool for formal verification of DSP assembly language programs
Formal verification has, in recent years, become widely used in the design and implementation of large integrated circuits, but its use in general software verification has been more limited. We have developed a new technique to verify assembly code for digital signal processors (DSPs) that makes...
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| Format: | Others |
| Language: | English |
| Published: |
2009
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| Online Access: | http://hdl.handle.net/2429/9415 |