Reducing post-silicon coverage monitoring overhead with emulation and statistical analysis

• Main Author: Ochoa Gallardo, Ricardo
• Language: English
• Published: University of British Columbia 2015
• Online Access: http://hdl.handle.net/2429/54393

With increasing design complexity, post-silicon validation has become a critical problem. In pre-silicon validation, coverage is the primary metric of validation effectiveness, but in post-silicon, the lack of observability makes coverage measurement problematic. On-chip coverage monitors are a possible solution, where a coverage monitor is a hardware circuit that sets to one when the coverage event of interest occurs. However, prior research has shown that the overhead is prohibitive for anything beyond a small number of coverage monitors. In this thesis, I explore techniques that reduce the number of instrumented coverage monitors, while still being able to imply full coverage with high probability. These techniques use a deterministic forward feature selection algorithm with the objective functions based on statistical information. For gathering the required statistical information, the method relies on emulation, where all coverage monitors of interest are instrumented on a version of the design. On this emulator, such as an FPGA, I stress the design with randomly generated tests to collect the data from the instrumented coverage monitors. I propose three objective functions for the feature selection algorithm: the first estimates the probability of a coverage monitor being set during a test; the next objective function builds a Bayesian Network (BN), then takes advantage of the relationship information between nodes (coverage monitors), which the network provides; the last objective function directly estimates the conditional probability of coverage from the gathered data. I demonstrate these techniques on a non-trivial system-on-chip, by measuring the code coverage achieved after executing randomly generated test programs. Depending on the objective function, results show a 67.7% to 95.5% reduction in the number of required coverage monitors. In the ASIC implementation, this would translate into an impact of 0.33-1.96% in silicon area overhead and 0.40-2.70% in static power overhead. These results show my technique works, by proving it is possible to track a smaller number of coverage events that statistically represent the whole set. === Applied Science, Faculty of === Electrical and Computer Engineering, Department of === Graduate